1. Field of the Invention
The present invention is directed in general to integrated circuit electrostatic discharge (ESD) protection devices and methods for operating same. In one aspect, the present invention relates to an ESD protection circuit that uses output transistors and diodes as ESD protection devices.
2. Description of the Related Art
An integrated circuit (IC) may be subject to an ESD event in the manufacturing process. during assembly and testing, or in the system application. Some on-chip ESD protection networks use an active MOSFET (metal oxide semiconductor field-effect transistor) rail clamp protection scheme with large ESD diodes between the input/output (I/O) pads and the power supply rails.
FIG. 1 illustrates in schematic diagram form a conventional ESD protection circuit 100 for protecting an I/O pad 116. The ESD protection circuit 100 is connected to a boost bus 101, a first power supply VDD 102, a trigger bus 103, a second power supply VSS 104, and a third power supply VSS_BULK 105. In the ESD protection circuit 100, a rail clamp device 117 has current electrodes coupled between the VDD 102 and VSS 104. Though shown as an NMOS MOSFET transistor, the rail clamp device 117 may be of a different type, for example, a PMOS transistor, a BJT (bipolar junction transistor), an SCR (silicon-controlled rectifier), or a GGMOS (grounded gate MOS) transistor. The ESD protection circuit 100 also includes a trigger circuit 118 that is coupled between the boost bus 101 and VSS 104 for providing a trigger signal 119 to the gate of the rail clamp transistor device 117. Other clamp trigger signals can also be provided on the trigger buss 103. As depicted, a first diode 110 is coupled between VDD 102 and the I/O pad 116, a second diode 112 is coupled between the boost bus 101 and the I/O pad 116, and a third diode 120 is coupled between the I/O pad 116 and the VSS 104. There are also first and second diodes 124, 126 coupled between VSS and VSS_BULK in opposite directions for purposes of providing additional ESD protection to and from the semiconductor substrate. To provide ESD protection for CMOS (complementary metal oxide semiconductor) I/O circuits, the ESD protection circuit 100 also includes a PMOS (P-type metal oxide semiconductor) output buffer transistor 114 and an NMOS (N-type metal oxide semiconductor) output buffer transistor 122 coupled to drive an internally generated signal on an I/O pad 116. The gates of output buffer transistors 114, 122 receive predriver signals PD.P, PD.N, respectively.
As will be appreciated, ESD diodes 110, 120 may be sized for conducting a relatively large ESD current, where ESD diode 110 provides a high-current ESD path from the I/O pad 116 to VDD in case of a positive ESD event on the I/O pad 116, and ESD diode 120 provides a high-current ESD path from VSS to I/O pad 116 in case of a negative ESD event on the I/O pad 116. During an ESD event that requires shunting a high ESD current from VDD to the VSS by rail clamp transistor device 117 (e.g., a positive ESD zap on I/O pad 116 with respect to another I/O pad), the trigger circuit 118 provides the voltage from boost bus 101 to the gate of rail clamp transistor device 117. ESD diode 112 provides a separate current path from the I/O pad 116 via the boost bus 101 to power trigger circuit 118. Since very little current is required to power trigger circuit 118, the voltage drop across ESD diode 112 during an ESD event is much smaller than the voltage drop across diode 110. In this manner, the boost bus 101 supplies a voltage that is higher than the VDD voltage 102 through the trigger circuit 118 to the gate of rail clamp transistor device 117 during an ESD event, thereby providing increased conductivity of the rail clamp device. The boost bus 101 can be relatively narrow due to the very little current it needs to conduct.